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Service Telephone:86-755-83294757
Trade Name:LCMXO2-1200ZE-3TG144C
Data Manual:
LCMXO2-1200ZE-3TG144C.pdf
Brand:Lattice
Particular Year:23+
Package:144-LQFP
Delivery Date:New and Original
Stock: 1000pcs
The LCMXO2-1200ZE-3TG144C has eight clock inputs, three pins on the left side, two each on the bottom and top, and one on the right side. Two each on the bottom and top, and one on the right side. These clock inputs drive the clock net. These eight inputs can be differential or single-ended, and can be used as a general-purpose I/O drive clock net if they are not being used to drive a clock net. When using single-ended clock inputs, only the PCLKT input can directly drive the clock tree. Low-density devices do not have edge clocks. Edge clocks are used for I/O register clocking and have low injection times and offsets. Edge clock inputs come from the PLL outputs, master clock pads, edge clock bridge outputs, and CIB sources. The eight master clock lines in the master clock network run throughout the device and can clock all resources within the device, including PFUs, EBRs, and PICs. All resources within the device, including the PFU, EBR, and PIC, can be clocked. In addition to the master clock signal, the LCMXO2-1200ZE-3TG144C has eight secondary high fan-out signals that can be used for global control signals such as clock enable, synchronisation or as global control signals.
Product Attributes
Total RAM bits: 65536
Number of I/Os: 107
Voltage - Supply: 1.14V ~ 1.26V
Mounting Type: Surface Mount
Operating Temperature: 0°C ~ 85°C (TJ)
Package/Case: 144-LQFP
Supplier Device Package: 144-TQFP (20x20)
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