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Trade Name:LCMXO2-256HC-6TG100C
Data Manual:LCMXO2-256HC-6TG100C.pdf
Brand:Lattice
Particular Year:23+
Package:32-QFN
Delivery Date:New and Original
Stock: 1000pcs
LCMXO2-256HC-6TG100C is designed on a 65 nm non-volatile low power process. The device architecture has several features such as programmable low swing differential I/O and the ability to turn off I/O banks, on-chip PLLs and oscillators dynamically.
LCMXO2-256HC-6TG100C The MachXO2™ family of ultra low power, instant-on, non-volatile PLDs has six devices with densities ranging from 256 to 6864 Look-Up Tables (LUTs).
Product Features
Six devices with 256 to 6864 LUT4s and 18 to 334 I/O
Advanced 65 nm low power process
As low as 22 μW standby power
Programmable low swing differential I/O
Stand-by mode and other power saving options
Up to 240 kbits sysMEM™ Embedded Block RAM
Up to 54 kbits Distributed RAM
Up to 256 kbits of User Flash Memory
Schmitt trigger inputs, up to 0.5 V hysteresis
I/O support hot socketing
On-chip differential termination
Programmable pull-up or pull-down mode
Eight primary clocks
Up to two edge clocks for high-speed I/O interfaces
Up to two analog PLLs per device with fractional-n frequency synthesis
Wide input frequency range (7 MHz to 400 MHz)
On-chip hardened functions: SPI, I2C, timer/counter
On-chip oscillator with 5.5% accuracy
Model
Brand
Package
Quantity
Describe
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