sales@hkmjd.com
Service Telephone:86-755-83294757
Trade Name:LFCPNX-100-7CBG256I
Data Manual:LFCPNX-100-7CBG256I.pdf
Brand:Lattice
Particular Year:23+
Package:256-LFBGA
Delivery Date:New original
Stock: 2000pcs
LFCPNX-100-7CBG256I low-power general purpose FPGAs featuring 10G SerDes, LPDDR4 memory interface support and up to 100k logic cells can be used in a wide range of applications across multiple markets.
Feature
Programmable architecture
50k to 100k logic cells
96 to 156 multipliers (18 × 18) in sysDSP™blocks
3.8 to 7.3 Mb of embedded memory(including EBR and LRAM)
170 to 299 programmable sysI/O (High Performance and Wide Range I/O)
Programmable sysI/O designed to support widevariety of interfaces
High Performance (HP) I/O supported onbottom I/O banks
Supports up to 1.8 V VCCIO
Mixed voltage support (1.0 V, 1.2 V, 1.5 V,and 1.8 V)
High-speed differential up to 1.5 Gbps
Wide Range (WR) I/O supported on left, right,and top I/O Banks
Supports up to 3.3 V VCCIO
Mixed voltage support: 1.2 V, 1.5 V, 1.8 V,2.5 V, and 3.3 V
Programmable slew rate: slow, medium,and fast
Controlled impedance mode
Emulated LVDS support
Hot Socketing Support
Embedded SerDes
From 625 Mbps up to 10.3125 Gbps perchannel, with up to 8 channels
Multiple Protocol PCS support
PCIe hard IP supports
Gen1, Gen2, and Gen3
Endpoint and Root complex
Multi-function up to four functions
Up to four lanes
SGMII at 1.25 Gbps and 2.5 Gbps
XAUI at 3.125 Gbps per lane
Power modes – Low Power mode and HighPerformance modes
User selectable
Low Power mode for power saving and/orthermal challenges
High Performance mode for faster processing
Small footprint package options
Three in 50k LC, and four in 100k LC
Programmable and dynamic phase control
Support spread spectrum clocking
sysDSP enhanced DSP blocks
Hardened pre-adder
Dynamic shift for AI/ML support
Four 18 × 18, eight 9 × 9, two 18 × 36, or 36 ×36 multipliers
Advanced 18 × 36, two 18 × 18, or four 8 × 8MAC per sysDSP blocks
Flexible memory resources
Up to 3.7 Mb sysMEM™ Embedded Block RAM(EBR) available
Programmable width
Error Correction Coding (ECC)
First In First Out (FIFO)
344 kbits to 639 kbits distributed RAM
Large RAM Blocks
0.5 Mbits per block
Up to seven (3.5 Mbit total) per device
Internal bus interface support
APB control bus
AHB-Lite for data bus
AXI4-streaming
Model
Brand
Package
Quantity
Describe
Xilinx
FCBGA-784
1000
FPGA, 154K+ Logic Cells 500MHz, 600MHz, 1.2GHz 784-FCBGA (23x23)
Intel
BGA-3184
2000
Embedded - System-on-Chip (SoC) IC Agilex I FPGA - 2.3M Logic Elements 1.4GHz 3184-BGA (56x45)
Intel
FBGA-1805
2000
Embedded - System-on-Chip (SoC) IC Agilex I FPGA - 2.3M Logic Elements 1.4GHz
Intel
FBGA-1805
5000
Embedded - System-on-Chip (SoC) IC Agilex I FPGA - 1.9M Logic Elements 1.4GHz
Intel
BGA-1805
5000
Embedded - System-on-Chip (SoC) IC Agilex I FPGA - 1.9M Logic Elements 1.4GHz 1805-BGA (42.5x42.5)
Intel
BGA-1805
5000
Embedded - System-on-Chip (SoC) IC Agilex I FPGA - 1.9M Logic Elements 1.4GHz 1805-BGA (42.5x42.5)
Intel
FBGA-1805
5000
Embedded - System-on-Chip (SoC) IC Agilex I FPGA - 1.9M Logic Elements 1.4GHz 1805-BGA (42.5x42.5)
Intel
FBGA-1805
5000
Embedded - System-on-Chip (SoC) IC Agilex I FPGA - 1.9M Logic Elements 1.4GHz 1805-BGA (42.5x42.5)
Intel
FBGA-1805
5000
Embedded - System-on-Chip (SoC) IC Agilex I FPGA - 1.9M Logic Elements 1.4GHz
Intel
FBGA-1805
5000
Embedded - System-on-Chip (SoC) IC Agilex I FPGA - 1.9M Logic Elements 1.4GHz
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